1. Field of the Invention
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having wafer level circuits and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. Referring to FIG. 1, the semiconductor package 1 has a silicon interposer 10 provided between a packaging substrate 18 and a semiconductor chip 11. The silicon interposer 10 has a plurality of through silicon vias (TSVs) 100 and an RDL (redistribution layer) structure 15 formed on the TSVs 100. The RDL structure 15 of the silicon interposer 10 is electrically connected to bonding pads 180 of the packaging substrate 18 through a plurality of conductive elements 17. The bonding pads 180 of the packaging substrate 18 have a large pitch therebetween. Further, an adhesive material 12 is formed to encapsulate the conductive elements 17. The TSVs 100 of the silicon interposer 10 is electrically connected to electrode pads 110 of the semiconductor chip 11 through a plurality of solder bumps 19. The electrode pads 110 have a small pitch therebetween. Further, an adhesive material 12 is formed to encapsulate the solder bumps 19.
Conventionally, if the semiconductor chip 11 is directly attached to the packaging substrate 18, a big CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chip 11 and the packaging substrate 18 adversely affects the formation of joints between the solder bumps 19 of the semiconductor chip 11 and the bonding pads 180 of the packaging substrate 18, thus easily resulting in delamination of the solder bumps 19 from the packaging substrate 18. On the other hand, along with increased integration of integrated circuits, the CTE mismatch between the semiconductor chip 11 and the packaging substrate 18 induces more thermal stresses and leads to more serious warpage, thereby reducing the reliability of electrical connection between the semiconductor chip 11 and the packaging substrate 18 and resulting in failure of a reliability test.
Therefore, the silicon interposer 10 close in material to the semiconductor chip 11 is disposed between the semiconductor chip 11 and the packaging substrate 18 so as to effectively overcome above-described drawbacks.
However, to form the TSVs 100 of the silicon interposer 10, a plurality of through holes need to be formed in the silicon interposer 10 and filled with metal, thus incurring a high fabrication cost. For example, for a 12-inch wafer, the TSV cost occupies about 40 to 50% of the total cost for fabricating the silicon interposer 10 (not including labor cost). Consequently, the cost of the final product is increased.
Further, the techniques for fabricating the silicon interposer 10 are difficult to perform, thus resulting in a low yield of the semiconductor package 1.
Therefore, how to overcome the above-described drawbacks has become critical.